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Harshit Agarwal
Assistant Professor

B.Tech. (2010, Birla Institute of Applied Sciences), Electronics and Communication Engineering
M.Tech. (2012, NIT Hamirpur), VLSI Design
Ph.D. (2017, Indian Institute of Technology Kanpur), Microelectronics
Post-Doc Fellow (2019, UC Berkeley)


IIT Jodhpur
NH 65 Nagaur Road
Karwar 342 037
Jodhpur District
(91 291) 280 1376
agarwalh@iitj.ac.in
http://home.iitj.ac.in/~agarwalh


Research Areas
  1. Industry standard compact modeling
  2. Analog and RF modeling
  3. Energy efficient next generation transistors
  4. emerging memories

      1. Selected Recent Publications
        1. H. Agarwal et.al., BSIM-IMG: Advanced Model for FDSOI Transistors with Back Channel Inversion, IEEE EDTM, Vol. , pp , 2020 , IEEE
        2. H. Agarwal et.al., Analytical Modeling and Experimental Validation of Threshold Voltage in BSIM6 MOSFET Model, IEEE Journal of the Electron Devices Society, Vol. 3, pp , 2015 , IEEE
        3. H. Agarwal et.al., Analytical Modeling of Flicker Noise in Halo Implanted MOSFETs, IEEE Journal of the Electron Devices Society, Vol. 3, pp , 2015 , IEEE
        4. H. Agarwal et.al., Analysis and modeling of flicker noise in lateral asymmetric channel mosfets, Solid-State Electronics, Vol. 115, pp , 2016 , Elsevier
        5. H. Agarwal et.al., Anomalous Transconductance in Long Channel Halo Implanted MOSFETs: Analysis and Modeling, IEEE Trans. Electron Devices, Vol. 64, pp , 2017 , IEEE
        6. H. Agarwal et.al., Designing 0.5 V 5-nm HP and 0.23 V 5-nm LP NC-FinFETs With Improved IOFF Sensitivity in Presence of Parasitic Capacitance, IEEE Trans. Electron Devices, Vol. 65, pp , 2018 , IEEE
        7. H. Agarwal et.al., Engineering Negative Differential Resistance in NCFETs for Analog Applications, IEEE Trans. Electron Devices, Vol. 65, pp , 2018 , IEEE
        8. H. Agarwal et.al., NCFET Design Considering Maximum Interface Electric Field, IEEE Electron Device Letters, Vol. 39, pp , 2018 , IEEE
        9. H. Agarwal et.al., Proposal for Capacitance Matching in Negative Capacitance Transistors, IEEE Electron Device Letters, Vol. 40, pp , 2019 , IEEE
        10. H. Agarwal et.al., BSIM-HV: High Voltage MOSFET Model Including Quasi-Saturation and Self-Heating Effect, IEEE Trans. Electron Devices, Vol. 66, pp , 2019 , IEEE